Datasheet

External Memory

1-8 ADSP-21369 EZ-KIT Lite Evaluation System Manual

Table 1-1 provides start and end addresses of the on-board external

memories.

Parallel flash memory, SDRAM, and SRAM are connected to the external

memory of the processor. To access SRAM and flash memories, use mem-

ory addressing via the respective memory bank or use the DMA controller.

SDRAM memory is connected to the SDRAM controller of the processor.

A set of programmable timing parameters is available to configure the

SDRAM banks to support slower memory accesses. Care must be taken

when configuring the SDRAM control registers. For more information

regarding the setup of the SDRAM controller, refer to the ADSP-21368

SHARC Processor Hardware Reference (includes ADSP-21369).

An example program is included in the EZ-KIT Lite installation directory

to demonstrate the controller setup.

SPI flash memory is connected to the SPI port of the processor; SPI flash

designates:

•DPI pin5 (DPI5) as a chip select

•DPI pin3 (

DPI3) as the SPI clock

•DPI pin1 (

DPI1) as the MOSI

•DPI pin2 (DPI2) as the MISO

Table 1-1. EZ-KIT Lite Evaluation Board External Memory

Start Address End Address Content

0x0020 0000 0x0027 FFFF SRAM memory (~MS0)

0x0400 0000 0x040F FFFF Flash memory (~MS1)

0x0800 0000 0x083F 0000 SDRAM memory (~MS2)

0x0C00 0000

0x0CFF FFFF

0x0FFF FFFF

Unused chip select (~MS3) for non-SDRAM addresses

Unused chip select (~MS3) for SDRAM addresses