Datasheet

ADXL345 Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
A 1 µF tantalum capacitor (C
S
) at V
S
and a 0.1 µF ceramic capacitor
(C
I/O
) at V
DD I/O
placed close to the ADXL345 supply pins is
recommended to adequately decouple the accelerometer from
noise on the power supply. If additional decoupling is necessary,
a resistor or ferrite bead, no larger than 100 Ω, in series with V
S
may be helpful. Additionally, increasing the bypass capacitance
on V
S
to a 10 µF tantalum capacitor in parallel with a 0.1 µF
ceramic capacitor may also improve noise.
Care should be taken to ensure that the connection from the
ADXL345 ground to the power supply ground has low impedance
because noise transmitted through ground has an effect similar
to noise transmitted through V
S
. It is recommended that V
S
and
V
DD I/O
be separate supplies to minimize digital clocking noise
on the V
S
supply. If this is not possible, additional filtering of
the supplies, as previously mentioned, may be necessary.
07925-016
ADXL345
GND
INT1
INT2
CS
SCL/SCLK
SDO/ALT ADDRESS
SDA/SDI/SDIO
3- OR 4-WIRE
SPI OR I
2
C
INTERFACE
V
S
V
S
C
S
V
DD I/O
V
DD I/O
C
IO
INTERRUPT
CONTROL
Figure 44. Application Diagram
MECHANICAL CONSIDERATIONS FOR MOUNTING
The ADXL345 should be mounted on the PCB in a location
close to a hard mounting point of the PCB to the case. Mounting
the
ADXL345 at an unsupported PCB location, as shown in
Figure 45, may result in large, apparent measurement errors
due to undampened PCB vibration. Locating the accelerometer
near a hard mounting point ensures that any PCB vibration at
the accelerometer is above the accelerometer’s mechanical sensor
resonant frequency and, therefore, effectively invisible to the
accelerometer. Multiple mounting points, close to the sensor,
and/or a thicker PCB also help to reduce the effect of system
resonance on the performance of the sensor.
MOUNTING POINTS
PCB
ACCELEROMETERS
07925-036
Figure 45. Incorrectly Placed Accelerometers
TAP DETECTION
The tap interrupt function is capable of detecting either single
or double taps. The following parameters are shown in Figure 46
for a valid single and valid double tap event:
x The tap detection threshold is defined by the THRESH_TAP
register (Address 0x1D).
x The maximum tap duration time is defined by the DUR
register (Address 0x21).
x The tap latency time is defined by the latent register
(Address 0x22) and is the waiting period from the end
of the first tap until the start of the time window, when a
second tap can be detected, which is determined by the
value in the window register (Address 0x23).
x The interval after the latency time (set by the latent register) is
defined by the window register. Although a second tap must
begin after the latency time has expired, it need not finish
before the end of the time defined by the window register.
FIRST TAP
TIME LIMIT FOR
TAPS (DUR)
LATENCY
TIME
(LATENT)
TIME WINDOW FOR
SECOND TAP (WINDOW)
SECOND TAP
SINGLE TAP
INTERRUPT
DOUBLE TAP
INTERRUPT
THRESHOLD
(THRESH_TAP)
X
HI BW
INTERRUPTS
07925-037
Figure 46. Tap Interrupt Function with Valid Single and Double Taps
If only the single tap function is in use, the single tap interrupt
is triggered when the acceleration goes below the threshold, as
long as DUR has not been exceeded. If both single and double
tap functions are in use, the single tap interrupt is triggered
when the double tap event has been either validated or
invalidated.
Rev. E | Page 28 of 40