Datasheet

ADXL345 Data Sheet
I
2
C
With
CS
tied high to V
DD I/O
, the ADXL345 is in I
2
C mode,
requiring a simple 2-wire connection, as shown in Figure 40.
The
ADXL345 conforms to the UM10204 I
2
C-Bus Specification
and User Manual, Rev. 03—19 June 2007, available from NXP
Semiconductors. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the bus parameters given in Table 11
and Table 12 are met. Single- or multiple-byte reads/writes are
supported, as shown in Figure 41. With the ALT ADDRESS pin
high, the 7-bit I
2
C address for the device is 0x1D, followed by
the R/
W
bit. This translates to 0x3A for a write and 0x3B for a
read. An alternate I
2
C address of 0x53 (followed by the R/
W
bit)
can be chosen by grounding the ALT ADDRESS pin (Pin 12).
This translates to 0xA6 for a write and 0xA7 for a read.
There are no internal pull-up or pull-down resistors for any
unused pins; therefore, there is no known state or default state
for the
CS
or ALT ADDRESS pin if left floating or unconnected.
It is required that the
CS
pin be connected to V
DD I/O
and that
the ALT ADDRESS pin be connected to either V
DD I/O
or GND
when using I
2
C.
Due to communication speed limitations, the maximum output
data rate when using 400 kHz I
2
C is 800 Hz and scales linearly with
a change in the I
2
C communication speed. For example, using I
2
C
at 100 kHz would limit the maximum ODR to 200 Hz. Operation
at an output data rate above the recommended maxi-mum may
result in undesirable effect on the acceleration data, including
missing samples or additional noise.
PROCESSOR
D IN/OUT
D OUT
R
P
V
DD I/O
R
P
ADXL345
CS
SDA
ALT ADDRESS
SCL
07925-008
Figure 40. I
2
C Connection Diagram (Address 0x53)
If other devices are connected to the same I
2
C bus, the nominal
operating voltage level of these other devices cannot exceed V
DD I/O
by more than 0.3 V. External pull-up resistors, R
P
, are necessary for
proper I
2
C operation. Refer to the UM10204 I
2
C-Bus Specification
and User Manual, Rev. 03—19 June 2007, when selecting pull-up
resistor values to ensure proper operation.
Table 11. I
2
C Digital Input/Output
Limit
1
Parameter Test Conditions Min Max Unit
Digital Input
Low Level Input Voltage (V
IL
) 0.3 × V
DD I/O
V
High Level Input Voltage (V
IH
) 0.7 × V
DD I/O
V
Low Level Input Current (I
IL
) V
IN
= V
DD I/O
0.1 µA
High Level Input Current (I
IH
) V
IN
= 0 V −0.1 µA
Digital Output
Low Level Output Voltage (V
OL
) V
DD I/O
< 2 V, I
OL
= 3 mA 0.2 × V
DD I/O
V
V
DD I/O
≥ 2 V, I
OL
= 3 mA 400 mV
Low Level Output Current (I
OL
)
V
OL
= V
OL, max
3
mA
Pin Capacitance f
IN
= 1 MHz, V
IN
= 2.5 V 8 pF
1
Limits based on characterization results; not production tested.
NOTES
1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.
2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS
SLAVE ACK ACK ACK
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS
SLAVE ACK ACK ACK ACK
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS
STOP
SLAVE ACK ACK
MASTER START
START
1
START
1
SLAVE ADDRESS + WRITE REGISTER ADDRESS NACK STOP
SLAVE ACK ACK
DATA
STOP
ACK
SINGLE-BYTE WRITE
MULTIPLE-BYTE WRITE
DATA
DATA
MULTIPLE-BYTE READ
SLAVE ADDRESS + READ
SLAVE ADDRESS + READ
ACK
DATA
DATA
DATA
STOP
NACK
ACK
SINGLE-BYTE READ
07925-033
Figure 41. I
2
C Device Addressing
Rev. E | Page 18 of 40