Datasheet

Data Sheet ADXL345
Table 9. SPI Digital Input/Output
Limit
1
Parameter Test Conditions Min Max Unit
Digital Input
Low Level Input Voltage (V
IL
) 0.3 × V
DD I/O
V
High Level Input Voltage (V
IH
)
0.7 × V
DD I/O
V
Low Level Input Current (I
IL
) V
IN
= V
DD I/O
0.1 µA
High Level Input Current (I
IH
) V
IN
= 0 V −0.1 µA
Digital Output
Low Level Output Voltage (V
OL
) I
OL
= 10 mA 0.2 × V
DD I/O
V
High Level Output Voltage (V
OH
) I
OH
= −4 mA 0.8 × V
DD I/O
V
Low Level Output Current (I
OL
) V
OL
= V
OL, max
10 mA
High Level Output Current (I
OH
) V
OH
= V
OH, min
−4 mA
Pin Capacitance f
IN
= 1 MHz, V
IN
= 2.5 V 8 pF
1
Limits based on characterization results, not production tested.
Table 10. SPI Timing (T
A
= 25°C, V
S
= 2.5 V, V
DD I/O
= 1.8 V)
1
Limit
2, 3
Parameter
Min
Max
Unit
Description
f
SCLK
5 MHz SPI clock frequency
t
SCLK
200 ns 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
t
DELAY
5 ns
CS falling edge to SCLK falling edge
t
QUIET
5 ns
SCLK rising edge to
CS rising edge
t
DIS
10
ns
CS rising edge to SDO disabled
t
CS,DIS
150 ns
CS deassertion between SPI communications
t
S
0.3 × t
SCLK
ns SCLK low pulse width (space)
t
M
0.3 × t
SCLK
ns SCLK high pulse width (mark)
t
SETUP
5 ns SDI valid before SCLK rising edge
t
HOLD
5 ns SDI valid after SCLK rising edge
t
SDO
40 ns SCLK falling edge to SDO/SDIO output transition
t
R
4
20 ns SDO/SDIO output high to output low transition
t
F
4
20 ns SDO/SDIO output low to output high transition
1
The
CS
, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
2
Limits based on characterization results, characterized with f
SCLK
= 5 MHz and bus load capacitance of 100 pF; not production tested.
3
The timing values are measured corresponding to the input thresholds (V
IL
and V
IH
) given in Table 9.
4
Output rise and fall times measured with capacitive load of 150 pF.
Rev. E | Page 17 of 40