Datasheet

ADXL345 Data Sheet
POWER SAVINGS
Power Modes
The ADXL345 automatically modulates its power consumption
in proportion to its output data rate, as outlined in Table 7. If
additional power savings is desired, a lower power mode is
available. In this mode, the internal sampling rate is reduced,
allowing for power savings in the 12.5 Hz to 400 Hz data rate
range at the expense of slightly greater noise. To enter low power
mode, set the LOW_POWER bit (Bit 4) in the BW_RATE register
(Address 0x2C). Table 8 shows the current consumption in low
power mode for cases where there is an advantage to using low
power mode. Use of low power mode for a data rate not shown
in Table 8 does not provide any advantage over the same data rate
in normal power mode. Therefore, it is recommended that only
data rates shown in Table 8 be used in low power mode. The
current consumption values shown in Table 7 and Table 8 are
for a V
S
of 2.5 V.
Table 7. Typical Current Consumption vs. Data Rate
(T
A
= 25°C, V
S
= 2.5 V, V
DD I/O
= 1.8 V)
Output Data
Rate (Hz) Bandwidth (Hz) Rate Code I
DD
(µA)
3200 1600 1111 140
1600
800
1110
90
800 400 1101 140
400 200 1100 140
200 100 1011 140
100 50 1010 140
50 25 1001 90
25
12.5
1000
60
12.5 6.25 0111 50
6.25 3.13 0110 45
3.13 1.56 0101 40
1.56 0.78 0100 34
0.78 0.39 0011 23
0.39 0.20 0010 23
0.20 0.10 0001 23
0.10 0.05 0000 23
Table 8. Typical Current Consumption vs. Data Rate,
Low Power Mode (T
A
= 25°C, V
S
= 2.5 V, V
DD I/O
= 1.8 V)
Output Data
Rate (Hz) Bandwidth (Hz) Rate Code I
DD
(µA)
400 200 1100 90
200
100
1011
60
100 50 1010 50
50 25 1001 45
25 12.5 1000 40
12.5 6.25 0111 34
Auto Sleep Mode
Additional power can be saved if the ADXL345 automatically
switches to sleep mode during periods of inactivity. To enable
this feature, set the THRESH_INACT register (Address 0x25)
and the TIME_INACT register (Address 0x26) each to a value
that signifies inactivity (the appropriate value depends on the
application), and then set the AUTO_SLEEP bit (Bit D4) and the
link bit (Bit D5) in the POWER_CTL register (Address 0x2D).
Current consumption at the sub-12.5 Hz data rates that are
used in this mode is typically 23 µA for a V
S
of 2.5 V.
Standby Mode
For even lower power operation, standby mode can be used. In
standby mode, current consumption is reduced to 0.1 µA (typical).
In this mode, no measurements are made. Enter standby mode
by clearing the measure bit (Bit D3) in the POWER_CTL register
(Address 0x2D). Placing the device into standby mode preserves
the contents of FIFO.
Rev. E | Page 14 of 40