Datasheet

ADV7623 Data Sheet
Rev. D | Page 6 of 16
Timing Diagrams
xDA
xCL
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
NOTES
1. x REFERS TO S, DDCA_S, DDCB_S, DDCC_S, DDCD_S.
08302-002
Figure 2. I
2
C Timing
0
8302-004
SCLK
LRCLK
I2S[3:0]
LEFT-JUSTIFIED
MODE
I2S[3:0]
RIGHT-JUSTIFIED
MODE
I2S[3:0]
I
2
S MODE
MSB MSB – 1
t
13
t
14
t
15
t
17
t
18
t
16
MSB
MSB – 1
LSBMSB
t
17
t
18
t
17
t
18
Figure 3. I
2
S Output Timing
08302-007
VALID DATA
VALID DATA
I2S[3:0],
LRCLK
SCLK
RISING EDGE
R0x0B[6] = 0
SCLK
FALLING EDGE
R0x0B[6] = 1
I2S[3:0]
LRCLK
t
19
t
20
t
19
t
20
Figure 4. I
2
S Input Timing