Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 98 of 108
ENHANCED DEFINITION
Table 85. ED Configuration Scripts
Input Format Input Data Width
1
Synchronization Format Input Color Space Output Color Space Table Number
525p at 59.94 Hz
8-bit DDR
EAV/SAV
YCrCb
YPrPb
Table 86
525p at 59.94 Hz 8-bit DDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 87
525p at 59.94 Hz 8-bit DDR EAV/SAV YCrCb RGB Table 88
525p at 59.94 Hz 16-bit SDR EAV/SAV YCrCb YPrPb Table 89
525p at 59.94 Hz 16-bit SDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 90
525p at 59.94 Hz 16-bit SDR EAV/SAV YCrCb RGB Table 91
525p at 59.94 Hz 16-bit SDR
HSYNC
/
VSYNC
YCrCb RGB Table 92
525p at 59.94 Hz 24-bit SDR EAV/SAV YCrCb YPrPb Table 93
525p at 59.94 Hz 24-bit SDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 94
525p at 59.94 Hz 24-bit SDR EAV/SAV YCrCb RGB Table 95
525p at 59.94 Hz 24-bit SDR
HSYNC
/
VSYNC
YCrCb RGB Table 96
525p at 59.94 Hz 24-bit SDR
HSYNC
/
VSYNC
RGB RGB Table 97
625p at 50 Hz 8-bit DDR EAV/SAV YCrCb YPrPb Table 98
625p at 50 Hz
8-bit DDR
HSYNC
/
VSYNC
YCrCb
YPrPb
Table 99
625p at 50 Hz 8-bit DDR EAV/SAV YCrCb RGB Table 100
625p at 50 Hz 8-bit DDR
HSYNC
/
VSYNC
YCrCb RGB Table 101
625p at 50 Hz 16-bit SDR EAV/SAV YCrCb YPrPb Table 102
625p at 50 Hz 16-bit SDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 103
625p at 50 Hz
16-bit SDR
EAV/SAV
YCrCb
RGB
Table 104
625p at 50 Hz 16-bit SDR
HSYNC
/
VSYNC
YCrCb RGB Table 105
625p at 50 Hz 24-bit SDR EAV/SAV YCrCb YPrPb Table 106
625p at 50 Hz 24-bit SDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 107
625p at 50 Hz 24-bit SDR EAV/SAV YCrCb RGB Table 108
625p at 50 Hz 24-bit SDR
HSYNC
/
VSYNC
YCrCb RGB Table 109
625p at 50 Hz 24-bit SDR
HSYNC
/
VSYNC
RGB RGB Table 110
1
SDR = single data rate; DDR = dual data rate.
Table 86. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 87. 8-Bit 525p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x00
525p at 59.94 Hz.
HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
0x31 0x01 Pixel data valid.
Table 88. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 89. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x30 0x04
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
D