Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 95 of 108
Table 65. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb and
CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0xFC All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Table 66. 8-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0xFC All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x8A 0x0C
Timing Mode 2 (slave).
HSYNC/VSYNC
synchronization.
Table 67. 8-Bit 525i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x80 0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Table 68. 8-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02
Software reset.
0x00 0xFC All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x80 0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 69. 16-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88 0x08 16-bit input enabled.
0x8A 0x0C
Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 70. 16-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset
0x00 0xFC All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x80 0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88 0x08 16-bit input enabled.
0x8A 0x0C
Timing Mode 2 (slave).
HSYNC/VSYNC
synchronization.
Table 71. 24-Bit 525i RGB In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0xFC All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x87 0x80 RGB input enabled.
0x88 0x10 24-bit RGB input enabled
0x8A 0x0C
Timing Mode 2 (slave).
HSYNC/VSYNC
synchronization.
D