Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 9 of 108
DIGITAL TIMING SPECIFICATIONS—3.3 V
V
DD
= 1.71 V to 1.89 V, PV
DD
= 1.71 V to 1.89 V, V
AA
= 2.6 V to 3.465 V, V
DD_IO
= 2.97 V to 3.63 V.
All specifications T
MIN
to T
MAX
(−40°C to +85°C), unless otherwise noted.
Table 8.
Parameter Conditions
1
Min Typ Max Unit
VIDEO DATA AND VIDEO CONTROL PORT
2, 3
Data Input Setup Time, t
11
4
SD 2.1 ns
ED/HD-SDR 2.3 ns
ED/HD-DDR 2.3 ns
ED (at 54 MHz)
1.7
ns
Data Input Hold Time, t
12
4
SD 1.0 ns
ED/HD-SDR 1.1 ns
ED/HD-DDR 1.1 ns
ED (at 54 MHz) 1.0 ns
Control Input Setup Time, t
11
4
SD 2.1 ns
ED/HD-SDR or ED/HD-DDR
2.3
ns
ED (at 54 MHz) 1.7 ns
Control Input Hold Time, t
12
4
SD 1.0 ns
ED/HD-SDR or ED/HD-DDR 1.1 ns
ED (at 54 MHz) 1.0 ns
Control Output Access Time, t
13
4
SD 12 ns
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 10 ns
Control Output Hold Time, t
14
4
SD 4.0 ns
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 3.5 ns
PIPELINE DELAY
5
SD
1
CVBS/YC Outputs (2×) SD oversampling disabled 68 Clock cycles
CVBS/YC Outputs (16×) SD oversampling enabled 67 Clock cycles
Component Outputs (2×) SD oversampling disabled 78 Clock cycles
Component Outputs (16×)
SD oversampling enabled
84
Clock cycles
ED
1
Component Outputs (1×) ED oversampling disabled 41 Clock cycles
Component Outputs (8×) ED oversampling enabled 46 Clock cycles
HD
1
Component Outputs (1×)
HD oversampling disabled
40
Clock cycles
Component Outputs (4×) HD oversampling enabled 44 Clock cycles
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2
Video data: C[7:0], Y[7:0], and S[7:0].
3
Video control:
P_HSYNC
,
P_VSYNC
,
P_BLANK
,
S_HSYNC
, and
S_VSYNC
.
4
Guaranteed by characterization.
5
Guaranteed by design.
D