Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 85 of 108
522 523 524 525
9
10 11
20 21 22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
283
284
285
ODD FIELD
EVEN
FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
5
7
6
4
3
2
1
8
HSYNC
VSYNC
HSYNC
VSYNC
06399-108
Figure 106. SD Slave Mode 2, NTSC
622 623 624 625
21 22 23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
DISPLAY
309 310 311 312 313 314 315 316
317
318 319
334 335 336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
DISPLAY
320
765
4
32
1
HSYNC
VSYNC
HSYNC
VSYNC
06399-109
Figure 107. SD Slave Mode 2, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV7342/ADV7343 can generate horizontal and vertical sync signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high indicates the start of an even field. The
ADV7342/ADV7343 automatically blank all normally blank lines as required by the CCIR-624 standard.
HSYNC
and
VSYNC
are output
on the
S_HSYNC
and
S_VSYNC
pins, respectively.
Cb
Y
PIXEL
DATA
HSYNC
VSYNC
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Y
Cr
06399-110
Figure 108. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
D