Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 84 of 108
622 623 624 625
21 22 23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
FIELD
DISPLAY
309 310 311 312 313 314 315 316
317
318 319
334 335 336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
DISPLAY
320
FIELD
5
7
6
4
3
2
1
HSYNC
HSYNC
06399-106
Figure 104. SD Slave Mode 1, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals. When
HSYNC
is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as
required by the CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions.
HSYNC
and
FIELD are output on the
S_HSYNC
and
S_VSYNC
pins, respectively.
FIELD
PIXEL
DATA
Cb Y
Cr Y
HSYNC
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
06399-107
Figure 105. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV7342/ADV7343 accept horizontal and vertical sync signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high indicates the start of an even field. The
ADV7342/ADV7343 automatically blank all normally blank lines as required by the CCIR-624 standard.
HSYNC
and
VSYNC
are input
on the
S_HSYNC
and
S_VSYNC
pins, respectively.
D