Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 75 of 108
TYPICAL APPLICATION CIRCUIT
06399-091
DAC 1
DAC 1
DAC 3
DAC1 TO DAC3 LOW DRIVE OPTION
R
SET1
AGND
4.12kΩ
75Ω
AGND
300Ω
ADA4411-3
DAC 2
LPF
DAC 2
75Ω
AGND
300Ω
ADA4411-3
LPF
DAC 3
75Ω
AGND
300Ω
ADA4411-3
LPF
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
S0
S1
S2
S3
S4
S5
S6
S7
DGNDPGND
DGNDPGND
0.1µF
GND_IO
0.01µF
GND_IO
33µF
GND_IO
10µF
GND_IO
FERRITE BEAD
V
DD_IO
V
DD_IO
POWER
SUPPLY
DECOUPLING
0.1µF
PGND
0.01µF
PGND
33µF
PGND
10µF
PGND
FERRITE BEAD
PV
DD
(1.8V)
PV
DD
POWER
SUPPLY
DECOUPLING
0.1µF
AGND
0.01µF
AGND
33µF
AGND
10µF
AGND
FERRITE BEAD
V
AA
V
AA
POWER
SUPPLY
DECOUPLING
0.1µF
DGND
0.01µF
DGND
33µF
AGND
10µF
DGND
FERRITE BEAD
V
DD
(1.8V)
V
DD
POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
V
DD_IO
PV
DD
V
AA
V
DD
ADV7342/ADV7343
1.235V
C0
C1
C2
C3
C4
C5
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
C6
C7
S_HSYNC
S_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
CLKIN_A
CLKIN_B
AGND
AGND
DGND
DGND
GND_IO
GND_IO
V
REF
AD1580
V
AA
1.1kΩ
OPTIONAL. IF THE INTERNAL VOLTAGE
REFERENCE IS USED, A 0.1µF CAPACITOR
SHOULD BE CONNECTED FROM V
REF
TO V
AA
.
0.1µF
COMP1
COMP2
V
AA
2.2nF
V
AA
2.2nF
EXT_LF2
EXT_LF1
12nF
150nF
170Ω
PV
DD
SDA
SCL
ALSB
PIXEL PORT INPUTS
CONTROL
INPUTS/OUTPUTS
UNUSED
CONNECT TO DGND
CLOCK INPUTS
I2C PORT
DGND
V
DD
EXTERNAL LOOP FILTERS
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PINS AND ON THE SAME
SIDE OF THE PCB AS THE
ADV7342/ADV7343.
R
SET1
R
SET2
AGND
4.12kΩ
510Ω
AGND
12nF
150nF
170Ω
1µF
AGND
DAC 1
DAC 2
DAC 3
AGND
75Ω
AGND
75Ω
AGND
75Ω
DAC 1
DAC 2
DAC 3
DAC1 TO DAC3 FULL DRIVE OPTION
OPTIONAL LPF
OPTIONAL LPF
OPTIONAL LPF
DAC 4
DAC 4
DAC 5
DAC 5
DAC 6
DAC 6
NOTES
1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS
CONNECTED TO THE COMP, R
SET
, V
REF
AND DAC OUTPUT
PINS SHOULD BE LOCATED CLOSE TO AND ON THE SAME
SIDE OF THE PCB AS THE ADV7342/ADV7343.
2. THE I
2
C DEVICE ADDRESS IS CONFIGURABLE USING THE
ALSB PIN:
ALSB = 0, I
2
C DEVICE ADDRESS = 0xD4 OR 0x54
ALSB = 1, I
2
C DEVICE ADDRESS = 0xD6 OR 0x56
ADI RECOMMENDS TO TIE ALSB TO VDD_IO. PLEASE
REFER TO POWER SUPPLY SEQUENCING SECTION FOR
MORE INFORMATION ON THIS.
3. THE RESISTORS CONNECTED TO THE R
SET
PINS SHOULD
HAVE A 1% TOLERANCE.
75Ω
AGND
300Ω
ADA4411-3
LPF
75Ω
AGND
300Ω
ADA4411-3
LPF
75Ω
AGND
300Ω
ADA4411-3
LPF
TIE EITHER LOW
OR HIGH
(SEE NOTE 2)
Figure 89. ADV7342/ADV7343 Typical Application Circuit
D