Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 69 of 108
Table 57.
S_VSYNC
Output Control
1, 2
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
ED/HD
VSYNC
Control
(Subaddress
0x34, Bit 2)
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
SD Sync Output
Enable
(Subaddress 0x02,
Bit 6)
Video Standard
Signal on
S_VSYNC
Pin
Duration
X X 0 0 X Tristate N/A
X X 0 1 Interlaced
Pipelined SD
VSYNC
/field
See the
SD Timing
section
0 0 1 x X
Pipelined ED/HD
VSYNC
or field signal
As per
VSYNC
or
field signal timing
1 0 1 X All HD interlaced
standards
Pipelined field signal
based on AV Code F bit
Field
1 0 1 X All ED/HD
progressive
standards
Pipelined
VSYNC
based
on AV Code V bit
Vertical blanking
interval
X 1 1 X All ED/HD
standards
except 525p
Pipelined ED/HD
VSYNC
based on the
vertical counter
Aligned with
serration lines
X 1 1 X 525p
Pipelined ED/HD
VSYNC
based on the vertical
counter
Vertical blanking
interval
1
In all ED/HD standards where there is a
VSYNC
output, the start of the
VSYNC
pulse is aligned with the falling edge of the embedded
VSYNC
in the output video.
2
X = don’t care.
LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power-sensitive applications, the ADV7342/ADV7343
support an Analog Devices proprietary low power mode of
operation on DAC 1, DAC 2, and DAC 3. To use this low power
mode, these DACs must be operating in full-drive mode (R
SET1
= 510 Ω, R
L
= 37.5 Ω). Low power mode is not available in low-
drive mode (R
SET
= 4.12 kΩ, R
L
= 300 Ω). Low power mode can
be independently enabled or disabled on DAC 1, DAC 2, and
DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is
disabled by default on each DAC.
In low power mode, DAC current consumption is content
dependent. On a typical video stream, it can be reduced by as
much as 40%. For applications requiring the highest possible video
performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10
The ADV7342/ADV7343 include an Analog Devices propri-
etary cable detection feature. The cable detection feature is
available on DAC 1 and DAC 2, while operating in full-drive
mode (R
SET1
= 510 Ω, R
L1
= 37.5 Ω, assuming a connected
cable). The feature is not available in low-drive mode (R
SET1
=
4.12 kΩ, R
L
= 300 Ω). For a DAC to be monitored, the DAC
must be powered up in Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, YC, YPrPb, and RGB output configurations.
For CVBS/YC output configurations, both DAC 1 and DAC 2
are monitored; that is, the CVBS and YC luma outputs are
monitored. For YPrPb and RGB output configurations, only
DAC 1 is monitored; that is, the luma or green output is
monitored.
Once per frame, the ADV7342/ADV7343 monitor DAC 1
and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,
respectively. If a cable is detected on one of the DACs, the
relevant bit is set to 0. If not, the bit is set to 1.
DAC AUTOPOWER-DOWN
Subaddress 0x10, Bit 4
For power-sensitive applications, a DAC autopower-down
feature can be enabled using Subaddress 0x10, Bit 4. This feature
is available only when the cable detection feature is enabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame. If they are unconnected,
some or all of the DACs automatically power down. Which
DAC or DACs are powered down depends on the selected
output configuration.
For CVBS/YC output configurations, if DAC 1 is unconnected,
only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and
DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is
unconnected, all three DACs power down. DAC 2 is not
monitored for YPrPb and RGB output configurations.
Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is
detected, the appropriate DAC or DACs remain powered up for
the duration of the frame. If no cable is detected, the appropriate
DAC or DACs power down until the next frame, when the process
is repeated.
D