Datasheet
ADV7342/ADV7343 Data Sheet
Rev. | Page 68 of 108
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input
pixel data or external synchronization signals provided on the
S_HSYNC
,
S_VSYNC
,
P_HSYNC
,
P_VSYNC
, and
P_BLANK
pins (see
Table 54). It is also possible to output synchronization signals on the
S_HSYNC
and
S_VSYNC
pins (see Table 55 to Table 57).
Table 54. Timing Synchronization Signal Input Options
Signal Pin Condition
SD
HSYNC
In
S_HSYNC
SD slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0])
1
SD
VSYNC
/FIELD In
S_VSYNC
SD slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0])
1
ED/HD
HSYNC
In
P_HSYNC
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
ED/HD
VSYNC
/FIELD In
P_VSYNC
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
ED/HD
BLANK
In
P_BLANK
1
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 55. Timing Synchronization Signal Output Options
Signal Pin Condition
SD
HSYNC
Out
S_HSYNC
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)
1
SD
VSYNC
/FIELD Out
S_VSYNC
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)
1
ED/HD
HSYNC
Out
S_HSYNC
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)
ED/HD
VSYNC
/FIELD Out
S_VSYNC
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)
1
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
Table 56.
S_HSYNC
Output Control
1, 2
ED/HD Input Sync
Format
(Subaddress
0x30, Bit 2)
ED/HD
HSYNC
Control
(Subaddress
0x34, Bit 1)
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
SD Sync
Output Enable
(Subaddress
0x02, Bit 6)
Signal on
S_HSYNC
Pin
Duration
X X 0 0 Tristate N/A
X X 0 1
Pipelined SD
HSYNC
See the
SD Timing section.
0 0 1 X
Pipelined ED/HD
HSYNC
As per
HSYNC
timing.
1 0 1 X
Pipelined ED/HD
HSYNC
based on
AV Code H bit
Same as line blanking
interval.
X 1 1 X
Pipelined ED/HD
HSYNC
based on
horizontal counter
Same as embedded
HSYNC
.
1
In all ED/HD standards where there is an
HSYNC
output, the start of the
HSYNC
pulse is aligned with the falling edge of the embedded
HSYNC
in the output video.
2
X = don’t care.
D