Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 55 of 108
SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
The ADV7342/ADV7343 support an SD square pixel mode
(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of
24.5454 MHz is required. The active resolution is 640 × 480. For
PAL operation, an input clock of 29.5 MHz is required. The
active resolution is 768 × 576.
For CVBS and S-Video (Y-C) outputs, the SD subcarrier
frequency registers must be updated to reflect the input clock
frequency used in SD square pixel mode. The SD input standard
autodetection feature must be disabled in SD square pixel
mode. In square pixel mode, the timing diagrams shown in
Figure 60 and Figure 61 apply.
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
Y
C
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
06399-064
Figure 60. Square Pixel Mode EAV/SAV Embedded Timing
FIELD
PIXEL
DATA
PAL = 308 CLOCK CYCLES
NTSC = 236 CLOCK CYCLES
Cb Y
Cr Y
HSYNC
06399-065
Figure 61. Square Pixel Mode Active Pixel Timing
D