Datasheet
ADV7342/ADV7343 Data Sheet
Rev. | Page 52 of 108
DESIGN FEATURES
OUTPUT OVERSAMPLING
The ADV7342/ADV7343 include two on-chip phase-locked
loops (PLLs) that allow for oversampling of SD, ED, and HD
video data. Table 41 shows the various oversampling rates
supported in the ADV7342/ADV7343.
SD Only, ED Only, and HD Only Modes
PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is
unused in these modes. PLL 1 is disabled by default and can be
enabled using Subaddress 0x00, Bit 1 = 0.
External Sync Polarity
For SD and ED/HD modes, the ADV7342/ADV7343 parts
typically expect HS and VS to be low during their respective
blanking periods. However, when the CEA861 compliance bit is
enabled (0x39, Bit 5 for ED/HD modes and 0x86, Bit 3 for SD
modes), the part expects the HS or VS to be active low or high,
depending on the input format selected (0x30 Bits [7:3]).
If a polarity other than the default is needed for ED/HD modes,
0x3A Bits [2:0] can be used to invert PHSYNCB, PVSYNCB or
PBLANKB individually, regardless of whether CEA-861-B mode is
enabled. It is not possible to invert S_HSYNC or S_VSYNC.
SD and ED/HD Simultaneous Modes
Both PLL 1 and PLL 2 are used in simultaneous modes. The use
of two PLLs allows for independent oversampling of SD and
ED/HD video. PLL 1 is used to oversample SD video data, and
PLL 2 is used to oversample ED/HD video data. In simultaneous
modes, PLL 2 is always enabled. PLL 1 is disabled by default and
can be enabled using Subaddress 0x00, Bit 1 = 0.
Table 41. Output Oversampling Modes and Rates
Input Mode
Subaddress 0x01 Bits[6:4]
PLL and Oversampling Control
Subaddress 0x00, Bit 1 Oversampling Mode and Rate
000 SD only 1 SD (2×)
000 SD only 0 SD (16×)
001/010 ED only 1 ED (1×)
001/010 ED only 0 ED (8×)
001/010 HD only 1 HD (1×)
001/010 HD only 0 HD (4×)
011/100 SD and ED 1 SD (2×) and ED (8×)
011/100 SD and ED 0 SD (16×) and ED (8×)
011/100 SD and HD 1 SD (2×) and HD (4×)
011/100 SD and HD 0 SD (16×) and HD (4×)
111
ED only (at 54 MHz)
1
ED only (at 54 MHz) (1×)
111 ED only (at 54 MHz) 0 ED only (at 54 MHz) (8×)
D