Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 50 of 108
Whether the ED/HD Y data is clocked in on the rising or falling
edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1]
(see the input sequence shown in Figure 52 and Figure 53).
CLKIN_A
CLKIN_B
S[7:0]
C[7:0]
Y[7:0]
HD
DECODER
S_HSYNC
P_VSYNC,
P_HSYNC,
P_BLANK
74.25MHz
8
CrCb
8
Y
3
2
YCrCb
27MHz
8
SD
DECODER
525p
OR
625p
06399-055
ADV7342/
ADV7343
S_VSYNC,
Figure 55. Simultaneous SD and ED Example Application
CLKIN_A
CLKIN_B
S[7:0]
C[7:0]
Y[7:0]
HD
DECODER
S_VSYNC,
S_HSYNC
P_VSYNC,
P_HSYNC,
P_BLANK
74.25MHz
8
CrCb
8
Y
3
2
YCrCb
27MHz
8
SD
DECODER
1080i
OR
720p
OR
1035i
06399-056
ADV7342/
ADV7343
Figure 56. Simultaneous SD and HD Example Application
ENHANCED DEFINITION ONLY (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
Enhanced definition (ED) YCrCb data can be input in an
interleaved 4:2:2 format on an 8-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the
P_HSYNC
,
P_VSYNC
, and
P_BLANK
pins.
The interleaved pixel data is input on Pin Y7 to Pin Y0, with
Pin Y0 being the LSB.
3FF 00 00 XY Cb0 Y0 Y1Cr0
CLKIN_A
Y[7:0]
06399-057
Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)
MPEG2
DECO
DER
CLKIN_A
Y[7:0]
54MHz
ADV7342/
ADV7343
P_VSYNC,
P_HSYNC,
P_BLANK
YCrCb
8
YCrCb
3
INTERLACED TO
PROGRESSIVE
06399-058
Figure 58. ED Only (at 54 MHz) Example Application
D