Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 48 of 108
INPUT CONFIGURATION
The ADV7342/ADV7343 support a number of different input
modes. The desired input mode is selected using Subaddress
0x01, Bits[6:4]. The ADV7342/ADV7343 default to standard
definition only (SD only) on power-up. Table 36 provides an
overview of all possible input configurations. Each input mode
is described in detail in the following sections.
STANDARD DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 000
Standard definition (SD) YCrCb data can be input in 4:2:2 format.
Standard definition (SD) RGB data can be input in 4:4:4 format.
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the
S_HSYNC
and
S_VSYNC
pins.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 0
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on
Subaddress 0x01, Bit 7), with Pin S0/Y0 being the LSB. The
ITU-R BT.601/656 input standard is supported. Embedded
EAV/SAV timing codes are also supported.
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on Subaddress
0x01, Bit 7), with Pin S0/Y0 being the LSB.
The CrCb pixel data is input on Pin Y7 to Pin Y0 (or Pin C7 to
Pin C0, depending on Subaddress 0x01, Bit 7), with Pin Y0/C0
being the LSB. Embedded EAV/SAV timing codes are not
supported, so an external synchronization is needed in this mode.
24-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
In 24-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to
Pin Y0, and the blue pixel data is input on Pin C7 to Pin C0.
The S0, Y0, and C0 pins are the respective bus LSBs.
Embedded EAV/SAV timing codes are not supported with SD
RGB mode. In addition, master timing mode is not supported
for SD RGB input mode; therefore, external synchronization
must be used.
Table 36. Input Configuration
S Y C
Input Mode
1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
000
SD only
Y/C/S bus swap (Subaddress 0x01[7]) = 0
8-bit YCrCb
2
YCrCb
16-bit YCrCb
2, 3
Y CrCb
Y/C/S bus swap (Subaddress 0x01[7]) = 1
8-bit YCrCb
2
YCrCb
16-bit YCrCb
2, 3
Y CrCb
SD RGB input enable (Subaddress 0x87[7]) = 1
24-bit RGB
3
R G B
001 ED/HD-SDR only
4, 5
ED/HD RGB input enable (Subaddress 0x35[1]) = 0
16-bit YCrCb Y CrCb
24-bit YCrCb Cr Y Cb
ED/HD RGB input enable (Subaddress 0x35[1]) = 1
24-bit RGB
3
R G B
010 ED/HD-DDR only (8-bit)
5
YCrCb
011 SD and ED/HD-SDR (24-bit)
5
YCrCb (SD) Y (ED/HD) CrCb (ED/HD)
100
SD and ED/HD-DDR (16-bit)
5
YCrCb (SD)
YCrCb (ED/HD)
111 ED only (54 MHz) (8-bit)
5
YCrCb
1
The input mode is determined by Subaddress 0x01, Bits[6:4].
2
In SD only (YCrCb) mode, the format of the input data is determined by Subaddress 0x88, Bits[4:3]. See Table 29 for more information.
3
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
4
In ED/HD-SDR only (YCrCb) mode, the format of the input data is determined by Subaddress 0x33, Bit 6. See Table 22 for more information.
5
ED = enhanced definition = 525p and 625p.
D