Datasheet
ADV7342/ADV7343 Data Sheet
Rev. | Page 46 of 108
SR7 to
Bit Number
1
Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
0xBB Field count Field count x x x Read only 0x0X
Reserved 0 0 0 Reserved
Encoder version code
0 0
Read only; first
encoder version
2
0 1
Read only; second
encoder version
1
x = Logic 0 or Logic 1.
2
See the HD Interlace External
P_HSYNC
and
P_VSYNC
Considerations section for information about the first encoder revision.
Table 33. Register 0xBD to Register 0xC8
SR7 to Bit Number
1
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0xBD SD CSC Matrix 1 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for a1 0x42
0xBE SD CSC Matrix 2 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for a2 0x81
0xBF SD CSC Matrix 3 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for a3 0x19
0xC0
SD CSC Matrix 4
SD CSC matrix coefficient
x
x
x
x
x
x
x
x
Bits [7:0] for a4
0x10
0xC1 SD CSC Matrix 5 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for b1 0x70
0xC2 SD CSC Matrix 6 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for b2 0x5E
0xC3 SD CSC Matrix 7 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for b3 0x12
0xC4 SD CSC Matrix 8 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for b4 0x80
0xC5 SD CSC Matrix 9 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for c1 0x26
0xC6 SD CSC Matrix 10 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for c2 0x4A
0xC7 SD CSC Matrix 11 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for c3 0x70
0xC8 SD CSC Matrix 12 SD CSC matrix coefficient x x x x x x x x Bits [7:0] for c4 0x80
1
x = Logic 0 or Logic 1.
Table 34. Register 0xC9 to Register 0xCE
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0xC9 Teletext control Teletext enable 0 Disabled. 0x00
1 Enabled.
Teletext request mode 0 Line request signal.
1 Bit request signal.
Teletext input pin
select
0 0
S_VSYNC
0 1
P_VSYNC
1 0 C0
1 1 Reserved
Reserved 0 0 0 0 Reserved
0xCA Teletext request
control
Teletext request falling
edge position control
0 0 0 0 0 clock cycles. 0x00
0 0 0 1 One clock cycle.
… … … … …
1 1 1 0 14 clock cycles.
1 1 1 1 15 clock cycles.
Teletext request rising
edge position control
0 0 0 0 0 clock cycles.
0 0 0 1 One clock cycle.
… … … … …
1 1 1 0 14 clock cycles.
1 1 1 1 15 clock cycles.
0xCB TTX Line Enable 0 Teletext on odd fields 22 21 20 19 18 17 16 15 Setting any of these bits
to 1 enables teletext on
the line number indicated
by the bit settings.
0x00
0xCC TTX Line Enable 1 Teletext on odd fields 14 13 12 11 10 9 8 7 0x00
0xCD TTX Line Enable 2 Teletext on even fields 22 21 20 19 18 17 16 15 0x00
0xCE TTX Line Enable 3 Teletext on even fields 14 13 12 11 10 9 8 7 0x00
D