Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 42 of 108
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x88 SD Mode
Register 7
Reserved 0 0x00
SD noninterlaced mode
0
Disabled.
1 Enabled.
SD double buffering 0 Disabled.
1 Enabled.
SD input format 0 0 8-bit YCbCr input.
0 1 16-bit YCbCr input.
1 0 16-bit RGB input.
1 1 Reserved.
SD digital noise reduction 0 Disabled.
1 Enabled.
SD gamma correction enable 0 Disabled.
1 Enabled.
SD gamma correction curve select 0 Gamma correction Curve A.
1 Gamma correction Curve B.
0x89 SD Mode
Register 8
SD undershoot limiter 0 0 Disabled. 0x00
0 1 −11 IRE.
1 0 −6 IRE.
1 1 −1.5 IRE.
Reserved 0 0 must be written to this bit.
SD black burst output on DAC luma 0 Disabled.
1 Enabled.
SD chroma delay 0 0 Disabled.
0 1 Four clock cycles.
1 0 Eight clock cycles.
1 1 Reserved.
Reserved 0 0 0 must be written to these bits.
1
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Table 30. Register 0x8A to Register 0x98
SR7 to Bit Number
1
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x8A SD Timing Register 0 SD slave/master mode 0 Slave mode. 0x08
1 Master mode.
SD timing mode 0 0 Mode 0.
1 1 Mode 3.
Reserved
1
SD luma delay 0 0 No delay.
0 1 Two clock cycles.
1 0 Four clock cycles.
1
1
Six clock cycles.
SD minimum luma value 0 −40 IRE.
1 −7.5 IRE.
SD timing reset 0
1
Normal operation.
Freezes the counters;
this bit must be set
back to zero in order to
reset the counters and
resume operation.
D