Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 40 of 108
Table 28. Register 0x80 to Register 0x83
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x80 SD Mode
Register 1
SD standard 0 0 NTSC 0x10
0 1 PAL B/D/G/H/I
1 0 PAL M
1 1 PAL N
SD luma filter
0
0
0
LPF NTSC
0 0 1 LPF PAL
0 1 0 Notch NTSC
0 1 1 Notch PAL
1 0 0 SSAF luma
1 0 1 Luma CIF
1 1 0 Luma QCIF
1 1 1 Reserved
SD chroma filter 0 0 0 1.3 MHz
0
0
1
0.65 MHz
0 1 0 1.0 MHz
0 1 1 2.0 MHz
1 0 0 Reserved
1 0 1 Chroma CIF
1 1 0 Chroma QCIF
1 1 1 3.0 MHz
0x82 SD Mode
Register 2
SD PrPb SSAF 0 Disabled 0x0B
1 Enabled
SD DAC Output 1 0 Refer to Table 37 in the Output
Configuration section
1
SD DAC Output 2 0 Refer to Table 37 in the Output
Configuration section
1
SD pedestal
0
Disabled
1 Enabled
SD square pixel mode 0 Disabled
1 Enabled
SD VCR FF/RW sync 0 Disabled
1 Enabled
SD pixel data valid 0 Disabled
1 Enabled
SD active video edge control 0 Disabled
1 Enabled
0x83 SD Mode
Register 3
SD pedestal on YPrPb
output
0 No pedestal on YPrPb 0x04
1 7.5 IRE pedestal on YPrPb
SD Output Levels Y
0
Y = 700 mV/300 mV
1 Y = 714 mV/286 mV
SD Output Levels PrPb 0 0 700 mV p-p (PAL), 1000 mV p-p (NTSC)
0 1 700 mV p-p
1 0 1000 mV p-p
1 1 648 mV p-p
SD VBI open 0 Disabled
1 Enabled
SD closed captioning field
control
0 0 Closed captioning disabled
0 1 Closed captioning on odd field only
1
0
Closed captioning on even field only
1 1 Closed captioning on both fields
Reserved 0 Reserved
D