Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 35 of 108
Table 23. Register 0x34 to Register 0x35
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x34 ED/HD Mode
Register 5
ED/HD timing reset 0 Internal ED/HD timing counters enabled 0x48
1 Resets the internal ED/HD timing counters
ED/HD
HSYNC
control
1
0
HSYNC
output control (refer to Table 56)
1
ED/HD
VSYNC
control
1
0
VSYNC
output control (refer to Table 57)
1
ED/HD blank polarity 0
P_BLANK
active high
1
P_BLANK
active low
ED Macrovision® enable 0 Macrovision disabled
1 Macrovision enabled
Reserved 0 0 must be written to this bit
ED/HD
VSYNC
/field input
0 0 = field input
1
1 =
VSYNC
input
Horizontal/vertical
counters
2
0 Update field/line counter
1 Field/line counter free running
0x35 ED/HD Mode
Register 6
Reserved 0 0x00
ED/HD RGB input enable 0 Disabled
1 Enabled
ED/HD sync on PrPb
0
Disabled
1
Enabled
ED/HD color DAC swap 0 DAC 2 = Pb, DAC 3 = Pr
1 DAC 2 = Pr, DAC 3 = Pb
ED/HD gamma
correction curve select
0 Gamma Correction Curve A
1 Gamma Correction Curve B
ED/HD gamma
correction enable
0 Disabled
1 Enabled
ED/HD adaptive filter
mode
0 Mode A
1 Mode B
ED/HD adaptive filter
enable
0
Disabled
1 Enabled
1
Used in conjunction with ED/HD sync in Subaddress 0x02, Bit 7, set to 1.
2
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
D