Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 34 of 108
Table 22. Register 0x31 to Register 0x33
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x31 ED/HD Mode
Register 2
ED/HD pixel data valid 0 Pixel data valid off. 0x00
1 Pixel data valid on.
Reserved 0
ED/HD test pattern enable 0 ED/HD test pattern off.
1 ED/HD test pattern on.
ED/HD test pattern hatch/field 0 Hatch.
1 Field/frame.
ED/HD VBI open 0 Disabled.
1 Enabled.
ED/HD undershoot limiter 0 0 Disabled.
0 1 −11 IRE.
1 0 −6 IRE.
1 1 −1.5 IRE.
ED/HD sharpness filter 0 Disabled.
1 Enabled.
0x32 ED/HD Mode
Register 3
ED/HD Y delay with respect to the
falling edge of
HSYNC
0 0 0 0 clock cycles. 0x00
0 0 1 One clock cycle.
0 1 0 Two clock cycles.
0 1 1 Three clock cycles.
1 0 0 Four clock cycles.
ED/HD color delay with respect to the
falling edge of
HSYNC
0 0 0 0 clock cycles.
0 0 1 One clock cycle.
0 1 0 Two clock cycles.
0 1 1 Three clock cycles.
1 0 0 Four clock cycles.
ED/HD CGMS 0 Disabled.
1 Enabled.
ED/HD CGMS CRC 0 Disabled.
1 Enabled.
0x33 ED/HD Mode
Register 4
ED/HD Cr/Cb sequence 0
Cb after falling edge of
HSYNC
.
0x68
1
Cr after falling edge of
HSYNC
Reserved 0 0 0 must be written to these bits.
Sinc compensation filter on DAC 1,
DAC 2, DAC 3
0 Disabled.
1 Enabled
Reserved 0 0 must be written to this bit.
ED/HD chroma SSAF 0 Disabled.
1 Enabled.
ED/HD chroma input 0 4:4:4.
1 4:2:2
ED/HD double buffering 0 Disabled.
1 Enabled.
D