Datasheet
Data Sheet ADV7342/ADV7343
Rev. | Page 33 of 108
Table 20. Register 0x12 to Register 0x17
SR7 to Bit Number
1
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x12 Pixel port readback (S bus) S[7:0] readback x x x x x x x x Read only. 0xXX
0x13 Pixel port readback (Y bus) Y[7:0] readback x x x x x x x x Read only. 0xXX
0x14 Pixel port readback (C bus) C[7:0] readback x x x x x x x x Read only. 0xXX
0x16 Control port readback P_BLANK
x Read only. 0xXX
P_VSYNC
x
P_HSYNC
x
S_VSYNC
x
S_HSYNC
x
SFL x
Reserved 0 0
0x17 Software reset Reserved 0 0x00
Software reset 0 Writing a 1 resets the device;
this is a self-clearing bit.
1
Reserved 0 0 0 0 0 0
1
x = Logic 0 or Logic 1.
Table 21. Register 0x30
SR7 to Bit Number
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Note
Value
0x30 ED/HD Mode
Register 1
ED/HD output standard 0 0 EIA770.2 output
EIA770.3 output
ED
HD
0x00
0 1 EIA770.1 output
1 0 Output levels for full input
range
1 1 Reserved
ED/HD input
synchronization format
0
External
HSYNC
,
VSYNC
and
field inputs
1
1 Embedded EAV/SAV codes
ED/HD standard
2
0 0 0 0 0 SMPTE 293M, ITU-BT.1358 525p at 59.94 Hz
0 0 0 1 0 BTA-1004, ITU-BT.1362 525p at 59.94 Hz
0 0 0 1 1 ITU-BT.1358 625p at 50 Hz
0 0 1 0 0 ITU-BT.1362 625p at 50 Hz
0 0 1 0 1 SMPTE 296M-1, SMPTE 274M-2 720p at 60/59.94 Hz
0 0 1 1 0 SMPTE 296M-3 720p at 50 Hz
0 0 1 1 1 SMPTE 296M-4, SMPTE 274M-5 720p at 30/29.97 Hz
0 1 0 0 0 SMPTE 296M-6 720p at 25 Hz
0 1 0 0 1 SMPTE 296M-7,
SMPTE 296M-8
720p at 24/23.98 Hz
0 1 0 1 0 SMPTE 240M 1035i at 60/59.94 Hz
0 1 0 1 1 Reserved
0 1 1 0 0 Reserved
0 1 1 0 1 SMPTE 274M-4,
SMPTE 274M-5
1080i at 30/29.97 Hz
0 1 1 1 0 SMPTE 274M-6 1080i at 25 Hz
0 1 1 1 1 SMPTE 274M-7,
SMPTE 274M-8
1080p at 30/29.97 Hz
1 0 0 0 0 SMPTE 274M-9 1080p at 25 Hz
1 0 0 0 1 SMPTE 274M-10,
SMPTE 274M-11
1080p at 24/23.98 Hz
1 0 0 1 0 ITU-R BT.709-5 1080Psf at 24 Hz
10011–11111
Reserved
1
Synchronization can be controlled with a combination of either
HSYNC
and
VSYNC
inputs or
HSYNC
and field inputs, depending on Subaddress 0x34, Bit 6.
2 See the HD Interlace External
P_HSYNC
and
P_VSYNC
Considerations section for more information.
D