Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 32 of 108
Table 19. Register 0x0A to Register 0x10
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x0A DAC 4, DAC 5, DAC 6
output levels
Positive gain to DAC output voltage 0 0 0 0 0 0 0 0 0% 0x00
0 0 0 0 0 0 0 1 +0.018%
0 0 0 0 0 0 1 0 +0.036%
0 0 1 1 1 1 1 1 +7.382%
0 1 0 0 0 0 0 0 +7.5%
Negative gain to DAC output voltage 1 1 0 0 0 0 0 0 7.5%
1 1 0 0 0 0 0 1 −7.382%
1 0 0 0 0 0 1 0 −7.364%
1 1 1 1 1 1 1 1 −0.018%
0x0B DAC 1, DAC 2, DAC 3
output levels
Positive gain to DAC output voltage 0 0 0 0 0 0 0 0 0% 0x00
0 0 0 0 0 0 0 1 +0.018%
0 0 0 0 0 0 1 0 +0.036%
0 0 1 1 1 1 1 1 +7.382%
0 1 0 0 0 0 0 0 +7.5%
Negative gain to DAC output voltage 1 1 0 0 0 0 0 0 −7.5%
1 1 0 0 0 0 0 1 −7.382%
1 0 0 0 0 0 1 0 −7.364%
1 1 1 1 1 1 1 1 −0.018%
0x0D DAC power mode DAC 1 low power enable 0 DAC 1 low power
disabled
0x00
1 DAC 1 low power
enabled
DAC 2 low power enable 0 DAC 2 low power
disabled
1 DAC 2 low power
enabled
DAC 3 low power enable 0 DAC 3 low power
disabled
1 DAC 3 low power
enabled
Reserved 0 0 0 0 0
0x10 Cable detection DAC 1 cable detect (read only) 0 Cable detected on
DAC 1
0x00
1 DAC 1 unconnected
DAC 2 cable detect (read only) 0 Cable detected on
DAC 2
1 DAC 2 unconnected
Reserved 0 0
Unconnected DAC autopower-down 0 DAC autopower-
down disable
1 DAC autopower-
down enable
Reserved 0 0 0
D