Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 19 of 108
Cb Y
Cr Y
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
Y7 TO Y0*
S_VSYNC
S_HSYNC
*SELECTED BY SUBADDRESS 0x01, BIT 7.
06399-018
Figure 18. SD Input Timing Diagram (Timing Mode 1)
t
3
t
3
t
4
t
7
t
8
t
5
SDA
SCL
t
1
t
2
t
6
06399-019
Figure 19. MPU Port Timing Diagram (I
2
C Mode)
D