Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 18 of 108
Y0 Y1
Y2 Y3
b
a
Cr2Cb2Cr0Cb
0
c
Y OUTPUT
P_HSYNC
P_VSYNC
P_BLANK
Y7 TO Y0
C7 TO C0
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
06399-016
Figure 16. HD-SDR, 16-Bit, 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Input Timing Diagram
Y7 TO Y0
Cb0 Y0
Cr0 Y1
b
a
P_HSYNC
P_VSYNC
P_BLANK
c
Y OUTPUT
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
06399-017
Figure 17. HD-DDR, 8-Bit, 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Input Timing Diagram
D