Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 17 of 108
Y0 Y1
Y2 Y3
b
a
Cr2Cb2Cr0Cb
0
c
Y OUTPUT
P_HSYNC
P_VSYNC
P_BLANK
Y7 TO Y0
C7 TO C0
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
06399-014
Figure 14. ED-SDR, 16-Bit, 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Input Timing Diagram
Y7 TO Y0
Cb0 Y0
Cr0 Y1
b
a
a = 32 CLOCK CYCLES FOR 525p
a = 24 CLOCK CYCLES FOR 625p
AS RECOMMENDED B
Y STANDARD
b(MIN) = 244 CLOCK CYCLES FOR 525p
b(MIN) = 264 CLOCK CYCLES FOR 625p
P_HSYNC
P_VSYNC
P_BLANK
c
Y OUTPUT
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING ED
GE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUTAFTER A TIME
EQUAL TO THE PIPELINE DELAY.
06399-015
Figure 15. ED-DDR, 8-Bit, 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Input Timing Diagram
D