Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 16 of 108
Cr2
Cr2
Y2Y1Cr0
EH/HD INPUT
SD INPUT
Cb2Y1Cr0
S7 TO S0
CLKIN_A
Y7 TO Y0
CLKIN_B
P_HSYNC,
P_VSYNC,
CONTROL
INPUTS
P_BLANK
S_HSYNC,
S_VSYNC
CONTROL
INPUTS
t
9
t
10
t
9
t
10
t
12
t
11
t
12
t
11
t
12
t
11
Y0
Cb0
Cb2
Cb0 Y0 Y2
06399-011
Figure 11. SD and ED/HD-DDR, 8-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 100)
CLKIN_A
Y7 TO Y0
CONTROL
OUTPUTS
Y1Cr0Y0Cb0 Cr2
Y2
Cb2
P_HSYNC,
P_VSYNC,
CONTROL
INPUTS
P_BLANK
t
9
t
10
t
12
t
11
t
13
t
14
06399-012
Figure 12. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Pixel Input Mode (Input Mode 111)
t
9
t
11
t
10
t
12
t
13
t
14
CLKIN_A
Y7 TO Y0
CONTROL
OUTPUTS
3FF 00 00 XY Cb0 Y0 Cr0 Y1
06399-013
Figure 13. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111)
D