Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 15 of 108
CLKIN_A*
Y7 TO Y0
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED
USING SUBADDRESS 0x01, BITS 1 AND 2.
CO
NT
RO
L
OU
TPUTS
Cr2Y2Cb2
Y1Cr0Y0Cb0
t
9
t
10
t
12
t
11
t
12
t
11
t
14
t
13
P_HSYNC,
P_VSYNC,
CONTROL
I
NPUTS
P_BLANK
06399-008
Figure 8. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Pixel Input Mode (Input Mode 010)
Y1Cr0Y0Cb0XY00003FF
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED
USING SUBADDRESS 0x01, BITS 1 AND 2.
CLKIN_A*
Y7 TO Y0
CONTROL
OUTPUTS
t
9
t
10
t
12
t
11
t
12
t
11
t
14
t
13
06399-009
Figure 9. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010)
t
9
t
10
t
9
t
10
t
11
t
11
Y0
Y1
Y2
Y3
Y4
Y5
ED/HD INPUT
SD INPUT
S7 TO S0
CLKIN_A
Y2Cb2Y1Cr0Y0Cb0
Cr4Cb4Cr2Cb2Cr0Cb0
Cr2
Y6
Cb6C7 TO C0
Y7 TO Y0
CLKIN_B
P_HSYNC,
P_VSYNC,
CONTROL
INPUTS
P_BLANK
S_HSYNC,
S_VSYNC
CONTROL
INPUTS
t
12
t
12
06399-010
Figure 10. SD and ED/HD-SDR, 16-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 011)
D