Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 14 of 108
Y0 Y1 Y2 Y3 Y4 Y5Y7 TO Y0
Cr4Cb4Cr2Cb2Cr0Cb0
CONTROL
OUTPUTS
CLKIN_A
P_HSYNC,
P_VSYNC,
CONTROL
INPUTS
P_BLANK
C7 TO C0
t
9
t
10
t
12
t
11
t
14
t
13
06399-005
Figure 5. ED/HD-SDR Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 001)
Y0 Y1 Y2 Y3 Y4 Y5
Cr4Cr3Cr2Cr1Cr0 Cr5
Cb4Cb3Cb2Cb1
Cb0
Cb5
Y7 TO Y0
CONTROL
OUTPUTS
CLKIN_A
P_HSYNC,
P_VSYNC,
CONTROL
INPUTS
P_BLANK
C7 TO C0
S7 TO S0
t
9
t
10
t
12
t
11
t
14
t
13
06399-006
Figure 6. ED/HD-SDR Only, 24-Bit, 4:4:4 YCrCb Pixel Input Mode (Input Mode 001)
CLKIN_A
C7 TO C0
G0 G1 G2 G3 G4 G5
B0 B1 B2 B3 B4 B5
R0 R1 R2 R3 R4 R5
Y7 TO Y0
CONTROL
OUTPUTS
S7 TO S0
P_HSYNC,
P_VSYNC,
CONTROL
INPUTS
P_BLANK
t
9
t
10
t
12
t
11
t
14
t
13
06399-007
Figure 7. ED/HD-SDR Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001)
D