Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 13 of 108
TIMING DIAGRAMS
The following abbreviations are used in Figure 2 to Figure 13:
• t
9
= clock high time
• t
10
= clock low time
• t
11
= data setup time
• t
12
= data hold time
• t
13
= control output access time
• t
14
= control output hold time
In addition, refer to Table 36 for the ADV7342/ADV7343 input
configuration.
t
9
CLKIN_A
t
10
CONTROL
OUTPUTS
S_HSYNC,
S_VSYNC
Cr2Cb2Cr0Cb0
*SELECTED BY SUBADDRESS 0x01, BIT 7.
IN MASTER/SLAVE MODE
IN SLAVE MODE
Y0 Y1 Y2
S7 TO S0/
Y7 TO Y0*
CONTROL
INPUTS
t
12
t
11
t
13
t
14
06399-002
Figure 2. SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
IN MASTER/SLAVE MODE
IN SLAVE MODE
CLKIN_A
CONTROL
OUTPUTS
S_HSYNC,
S_VSYNC
*SELECTED BY SUBADDRESS 0x01, BIT 7.
S7 TO S0/
Y7 TO Y0*
Y7 TO Y0/
C7 TO C0*
CONTROL
INPUTS
t
9
t
10
Cr2
Cb2
Cr0Cb0
Y0 Y1
Y2
Y3
t
12
t
14
t
11
t
13
06399-003
Figure 3. SD Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
C7 TO C0
Y7 TO Y0
CONTROL
OUTPUTS
S7
TO S0
t
9
CLKIN_A
t
10
S_HSYNC,
S_VSYNC
CONTROL
INPUTS
t
11
G0 G1 G2
B0 B1 B2
R0 R1 R2
t
12
t
14
t
13
06399-004
Figure 4. SD Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000)
D