Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 11 of 108
MPU PORT TIMING SPECIFICATIONS
V
DD
= 1.71 V to 1.89 V, PV
DD
= 1.71 V to 1.89 V, V
AA
= 2.6 V to 3.465 V, V
DD_IO
= 1.71 V to 3.63 V.
All specifications T
MIN
to T
MAX
(−40°C to +85°C), unless otherwise noted.
Table 10.
Parameter Conditions Min Typ Max Unit
MPU PORT, I
2
C MODE
1
See Figure 19
SCL Frequency 0 400 kHz
SCL High Pulse Width, t
1
0.6 µs
SCL Low Pulse Width, t
2
1.3 µs
Hold Time (Start Condition), t
3
0.6
µs
Setup Time (Start Condition), t
4
0.6 µs
Data Setup Time, t
5
100 ns
SDA, SCL Rise Time, t
6
300 ns
SDA, SCL Fall Time, t
7
300 ns
Setup Time (Stop Condition), t
8
0.6 µs
1
Guaranteed by characterization.
POWER SPECIFICATIONS
V
DD
= 1.8 V, PV
DD
= 1.8 V, V
AA
= 3.3 V, V
DD_IO
= 3.3 V, T
A
= +25°C.
Table 11.
Parameter Conditions Min Typ Max Unit
NORMAL POWER MODE
1, 2
I
DD
3
SD only (16× oversampling) 90 mA
ED only (8× oversampling)
4
65 mA
HD only (4× oversampling)
4
91 mA
SD (16× oversampling) and ED (8× oversampling) 95 mA
SD (16× oversampling) and HD (4× oversampling) 122 mA
I
DD_IO
1 mA
I
AA
5
Three DACs enabled (ED/HD only)
124
mA
Six DACs enabled (SD only and simultaneous modes ) 140 mA
I
PLL
SD only, ED only, or HD only modes 5 mA
Simultaneous modes 10 mA
SLEEP MODE
I
DD
5 µA
I
AA
0.3 µA
I
DD_IO
0.2 µA
I
PLL
0.1 µA
1
R
SET1
= 510 Ω (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). R
SET2
= 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode).
2
75% color bar test pattern applied to pixel data pins.
3
I
DD
is the continuous current required to drive the digital core.
4
Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5
I
AA
is the total current required to supply all DACs.
D