Datasheet

Data Sheet ADV7342/ADV7343
Rev. | Page 105 of 108
Table 136. 24-Bit 1080i YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x68
1080i at 30 Hz/29.97 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
0x33 0x28 4:4:4 input data.
Table 137. 24-Bit 1080i RGB In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x68
1080i at 30 Hz/29.97 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
0x33 0x28 4:4:4 input data.
0x35 0x02 RGB input enabled.
D