Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 104 of 108
Table 128. 8-Bit 1080i YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01 0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x68
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 129. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x30 0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 130. 16-Bit 1080i YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30 0x68
1080i at 30 Hz/29.97 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 131. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 132. 16-Bit 1080i YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x68
1080i at 30 Hz/29.97 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 133. 24-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x30 0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
0x33
0x28
4:4:4 input data.
Table 134. 24-Bit 1080i YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x30 0x68
1080i at 30 Hz/29.97 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
0x33 0x28 4:4:4 input data.
Table 135. 24-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x02
Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
0x33 0x28 4:4:4 input data.
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