Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 102 of 108
Table 112. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 113. 8-Bit 720p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x02
Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01 0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x28
720p at 60 Hz/59.94 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output
levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 114. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01 0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 115. 8-Bit 720p YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01
0x20
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x28
720p at 60 Hz/59.94 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output
levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 116. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x30 0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 117. 16-Bit 720p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01 0x10 HD-SDR input mode.
0x30 0x28
720p at 60 Hz/59.94 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 118. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x2C
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
Table 119. 16-Bit 720p YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x28
720p at 60 Hz/59.94 Hz.
HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31 0x01 Pixel data valid. 4× oversampling.
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