Datasheet

ADV7342/ADV7343 Data Sheet
Rev. | Page 100 of 108
Table 99. 8-Bit 625p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x18
625p at 50 Hz.
HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
0x31 0x01 Pixel data valid.
Table 100. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x1C
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 101. 8-Bit 625p YCrCb In, RGB Out
Subaddress
Setting
Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x18
625p at 50 Hz.
HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
0x31 0x01 Pixel data valid.
Table 102. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x30 0x1C
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 103. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x02
Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x30 0x18
625p at 50 Hz.
HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 104. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 105. 16-Bit 625p YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x18
625p at 50 Hz.
HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 106. 24-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x30 0x1C
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33 0x28 4:4:4 input data.
Table 107. 24-Bit 625p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x30 0x18
625p at 50 Hz.
HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
0x33 0x28 4:4:4 input data.
Table 108. 24-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
0x33
0x28
4:4:4 input data.
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