Datasheet

ADV7320/ADV7321
Rev. A | Page 9 of 88
TIMING DIAGRAMS
t
9
t
11
CLKIN_A
C9–C0
t 10
t
12
CONTROL
INPUTS
Y0 Y1 Y2 Y3 Y4 Y5
Y9–Y0
t
14
CONTROL
OUTPUTS
t
13
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
P_HSYNC,
P_VSYNC,
P_BLANK
Cr4
Cb4
Cr2Cb2
Cr0
Cb0
05067-003
Figure 3. HD Only 4:2:2 Input Mode (Input Mode 010); PS Only 4:2:2 Input Mode (Input Mode 001)
t
9
t
11
CLKIN_A
C9–C0
t
10
t
12
C
ONTROL
INPUTS
Y0 Y1 Y2 Y3 Y4 Y5
Y9–Y0
t
14
CONTROL
OUTPUTS
t
13
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
S9–S0
Cr4Cr3
Cr2Cr1
Cr0
Cr5
Cb4Cb3
Cb2Cb1
Cb0
Cb5
P_HSYNC,
P_VSYNC,
P_BLANK
05067-004
Figure 4. HD Only 4:4:4 Input Mode (Input Mode 010); PS Only 4:4:4 Input Mode (Input Mode 001)