Datasheet

ADV7320/ADV7321
Rev. A | Page 80 of 88
MODE 3—MASTER/SLAVE OPTION
(TIMING REGISTER 0 TR0 =
X X X X X 1 1 0 OR X X X X X 1 1 1)
In this mode, the ADV7320/ADV7321 accept or generate hori-
zontal sync and odd/even field signals. When
HSYNC
is high, a
transition of the field input indicates a new frame, that is, vertical
retrace. The
BLANK
signal is optional. When the
BLANK
input
is disabled, ADV7320/ADV7321 automatically blank all normally
blank lines as per CCIR-624.
HSYNC
,
BLANK
, and
VSYNC
are
output in master mode and input in slave mode on
S_VSYNC
,
S_BLANK
, and
S_VSYNC
, respectively.
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
283
284
285
ODD FIELD EVEN FIELD
DISPLAY DISPLAY
VERTICAL BLANK
522 523 524 525
9
10 11
20 21 22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
HSYNC
BLANK
FIELD
05067-120
HSYNC
BLANK
FIELD
8
765
4
32
1
Figure 120. SD Timing Mode 3 (NTSC)
622 623 624 625
5
6212223
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
FIELD
DISPLAY
309 310 311 312 313 314 315 316
317
318 319
334 335 336
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
FIELD
DISPLAY
320
4
32
1
7
HSYNC
BLANK
HSYNC
BLANK
05067-121
Figure 121. SD Timing Mode 3 (PAL)