Datasheet

ADV7320/ADV7321
Rev. A | Page 8 of 88
TIMING SPECIFICATIONS
V
AA
= 2.375 V to 2.625 V, V
DD
= 2.375 V to 2.625 V, V
DD_IO
= 2.375 V to 3.6 V, V
REF
= 1.235 V, R
SET
= 3040 Ω, R
LOAD
= 300 Ω. All
specifications T
MIN
to T
MAX
(0°C to 70°C), unless otherwise noted.
Table 4.
Parameter Min Typ Max Unit Test Conditions
MPU PORT
1
SCLOCK Frequency 0 400 kHz
SCLOCK High Pulse Width, t
1
0.6 µs
SCLOCK Low Pulse Width, t
2
1.3 µs
Hold Time (Start Condition), t
3
0.6 µs
First clock generated after this period relevant for
repeated start condition
Setup Time (Start Condition), t
4
0.6 µs
Data Setup Time, t
5
100 ns
SDATA, SCLOCK Rise Time, t
6
300 ns
SDATA, SCLOCK Fall Time, t
7
300 ns
Setup Time (Stop Condition), t
8
0.6 µs
RESET Low Time
100 ns
ANALOG OUTPUTS
Analog Output Delay
2
7 ns
Output Skew 1 ns
CLOCK CONTROL AND PIXEL PORT
3
f
CLK
29.5 MHz SD PAL square pixel mode
f
CLK
81 MHz PS/HD async mode
Clock High Time, t
9
40 % of one clock cycle
Clock Low Time, t
10
40 % of one clock cycle
Data Setup Time, t
11
1
2.0 ns
Data Hold Time, t
12
1
2.0 ns
SD Output Access Time, t
13
15 ns
SD Output Hold Time, t
14
5.0 ns
HD Output Access Time, t
13
14 ns
HD Output Hold Time, t
14
5.0 ns
PIPELINE DELAY
4
63 Clock cycles SD (2×, 16×)
76 Clock cycles SD component mode (16×)
35 Clock cycles PS (1×)
41 Clock cycles PS (8×)
36 Clock cycles HD (2×, 1×)
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: C[9:0], Y[9:0], S[9:0]; Control:
P_HSYNC
,
P_VSYNC
,
P_BLANK
,
S_HSYNC
,
S_VSYNC
,
S_BLANK
.
4
SD, PS = 27 MHz; HD = 74.25 MHz.