Datasheet

ADV7320/ADV7321
Rev. A | Page 77 of 88
MODE 1—MASTER OPTION
(TIMING REGISTER 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7320/ADV7321 can generate horizontal
sync and odd/even field signals. When
HSYNC
is low, a transition
of the field input indicates a new frame, that is, vertical retrace.
The
BLANK
signal is optional. When the
BLANK
input is disabled,
ADV7320/ADV7321 automatically blank all normally blank lines
as per CCIR-624. Pixel data is latched on the rising clock edge
following the timing signal transitions.
HSYNC
,
BLANK
, and
FIELD are output on
S_HSYNC
,
S_BLANK
, and
S_VSYNC
,
respectively.
622 623 624 625
21 22 23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
FIELD
DISPLAY
309 310 311 312 313 314 315 316
317
318 319
334 335 336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
DISPLAY
320
FIELD
5
7
6
4
3
2
1
HSYNC
BLANK
HSYNC
BLANK
05067-114
Figure 114. SD Slave Mode 1 (PAL)
FIELD
PIXEL
DATA
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
Cb Y
Cr Y
HSYNC
BLANK
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
05067-115
Figure 115. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave