Datasheet

ADV7320/ADV7321
Rev. A | Page 72 of 88
The register settings in Table 41 are used to generate an SD NTSC
CVBS output on DAC A, S-video on DACs B and C, and YPrPb
on DACs D, E, and F. Upon power-up, the subcarrier registers
are programmed with the appropriate values for NTSC. All
other registers are set as normal/default.
Table 41. NTSC Test Pattern Register Writes
Subaddress Register Setting
0x00 0xFC
0x40 0x10
0x42 0x40
0x44 0x40 (internal test pattern on)
0x4A 0x08
For PAL CVBS output on DAC A, the same settings are used,
except Subaddress 0x40 is programmed to 0x11 and the F
SC
registers are programmed as shown in
Table 42.
Table 42. PAL F
SC
Register Writes
Subaddress Description Register Setting
0x4C F
SC
0 0xCB
0x4D F
SC
1 0x8A
0x4E F
SC
2 0x09
0x4F F
SC
3 0x2A
Note that when programming the F
SC
registers, the user must
write the values in the sequence F
SC
0, F
SC
1, F
SC
2, F
SC
3. The full
F
SC
value is only accepted after the F
SC
3 write is complete.
The register settings in
Table 43 are used to generate a 525p
hatch pattern on DAC D, E, and F. All other registers are set as
normal/default.
Table 43. 525p Test Pattern Register Writes
Subaddress Register Setting
Ox00 0xFC
0x01 0x10
0x10 0x00
0x11 0x05
0x16 0xA0
0x17 0x80
0x18 0x80
For 625p hatch pattern on DAC D, the same register settings are
used except Subaddress 0x10 = 0x18.