Datasheet

ADV7320/ADV7321
Rev. A | Page 64 of 88
Analog Signal Interconnect
Locate the ADV7320/ADV7321 as close as possible to the output
connectors to minimize noise pickup and reflections due to
impedance mismatch.
For optimum performance, each analog output should be
source- and load-terminated, as shown in
Figure 91. The
termination resistors should be as close as possible to the
ADV7320/ADV7321 to minimize reflections.
For optimum performance, it is recommended that all decoupling
and external components relating to the ADV7320/ADV7321 are
located on the same side of the PCB and as close as possible to
the ADV7320/ADV7321. Unused inputs should be tied to ground.
5kΩ
V
DD_IO
5kΩ
V
DD_IO
COMP1, 2
45
V
AA
41
V
DD
V
DD_IO
1
ADV7320/
ADV7321
I
2
C
19
50
49
48
23
CLKIN_B
63
24
25
33
CLKIN_A
32
EXT_LF
34
UNUSED
INPUTS
SHOULD BE
GROUNDED
C0–C9
S0–S9
Y0–Y9
V
AA
4
.7μF
+
4.7k
Ω
820pF
3.9nF
V
AA
GND_ IO
64
AGND
40
DGND
11, 57
I
2
C BUS
10nF 0.1μF
10nF 0.1μF
10, 56
V
DD_IO
V
DD
10nF 1μF
V
AA
+
V
AA
0.1μF
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
36
V
AA
0.1μF
DAC D
39
DAC E
38
DAC F
37
DAC A
44
DAC B
43
DAC C
42
V
REF
46
1.1kΩ
V
AA
RECOMMENDED EXTERNAL
AD1580 FOR OPTIMUM
PERFORMANCE
5k
Ω
V
DD_IO
SCLK
22
100Ω
680Ω
SDA
21
ALSB
20
R
SET1
R
SET2
47
100Ω
3040Ω
SELECTION HERE
DETERMINES
DEVICE ADDRESS
35
3040Ω
5kΩ
V
DD_IO
S_HSYNC
S_VSYNC
S_BLANK
P_HSYNC
P_VSYNC
P_BLANK
RESET
05067-091
100nF
A
LL COMPONENTS IN DASHED BOXES MUST BE LOCATED ON THE SAME SID
E
O
F THE PCB AS THE ADV7320/ADV7321 AND AS CLOSE AS POSSIBLE TO THE ADV7320/ADV7321
.
300Ω
300Ω
300Ω
300Ω
300Ω
300Ω
Figure 91. ADV7320/ADV7321 Circuit Layout