Datasheet

ADV7320/ADV7321
Rev. A | Page 47 of 88
SQUARE PIXEL TIMING MODE
[Address 0x42, Bit 4]
In square pixel mode, the following timing diagrams apply.
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
Y
C
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
05067-040
Figure 64. EAV/SAV Embedded Timing
FIELD
PIXEL
DATA
PAL = 44 CLOCK CYCLES
NTSC = 44 CLOCK CYCLES
PAL = 308 CLOCK CYCLES
NTSC = 236 CLOCK CYCLES
Cb Y
Cr Y
05067-041
HSYNC
BLANK
Figure 65. Active Pixel Timing