Datasheet

ADV7320/ADV7321
Rev. A | Page 45 of 88
RESET SEQUENCE
A reset is activated with a high-to-low transition on the
RESET
pin (Pin 33) according to the timing specifications, and the
ADV7320/ADV7321 revert to the default output configuration.
Figure 63 illustrates the
RESET
timing sequence.
SD VCR FF/RW SYNC
[Subaddress 0x42, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit [Subaddress 0x42,
Bit 5] can be used for nonstandard input video, that is, in fast
forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields are reached; in rewind mode, this sync
signal usually occurs after the total number of lines/fields are
reached. Conventionally this means that the output video will
have corrupted field signals because one signal is generated by
the incoming video and another is generated when the internal
lines/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled, the line/field
counters are updated according to the incoming
VSYNC
signal,
and the analog output matches the incoming
VSYNC
signal.
This control is available in all slave timing modes except Slave
Mode 0.
XXXXXX
XXXXXX
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
RESET
DIGITAL TIMING
DACs
A, B, C
PIXEL DATA
VALID
05067-039
Figure 63.
RESET
Timing Sequence