Datasheet

ADV7320/ADV7321
Rev. A | Page 44 of 88
NO F
SC
RESET APPLIED
F
SC
PHASE = FIELD 4 OR 8
307 310 313 320
DISPLAY
START OF FIELD 4 OR 8
F
SC
RESET APPLIED
F
SC
RESET PULSE
F
SC
PHASE = FIELD 1
307 310 313 320
DISPLAY
START OF FIELD 4 OR 8
05067-037
Figure 61. Subcarrier Reset Timing Diagram
LCC1
GLL
P19–P10
ADV7183A
VIDEO
DECODER
COMPOSITE
VIDEO
1
CLKIN_A
RTC_SCR_TR
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
Y9–Y0/S9–S0
5
RTC
LOW
H/L TRANSITION
COUNT START
128
TIME SLOT 01
13 0
14 BITS
SUBCARRIER
PHASE
14
21
19
F
SC
PLL INCREMENT
2
VALID
SAMPLE
INVALID
SAMPLE
6768
4 BITS
RESERVED
0
SEQUENCE
BIT
3
RESET
BIT
4
RESERVED
ADV7320/
ADV7321
NOTES
1
FOR EXAMPLE, VCR OR CABLE.
2
F
SC
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7320/ADV7321 F
SC
DDS REGISTER IS F
SC
. PLL INCREMENTS BITS 21:0
AND BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7320/ADV7321.
3
SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE.
4
RESET ADV7320/ADV7321 DDS.
5
SELECTED BY REGISTER ADDRESS 0x01, BIT 7.
05067-038
8/LINE-
LOCKED
CLOCK
5 BITS
RESERVED
Figure 62. RTC Timing and Connections