Datasheet
ADV7320/ADV7321
Rev. A | Page 34 of 88
Table 17. Registers 0x4A to 0x58
SR7–
SR0
Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
Value
0x4A SD Slave/Master Mode 0 Slave mode. 0x08
SD Timing
Register 0
1 Master mode.
SD Timing Mode 0 0 Mode 0.
0 1 Mode 1.
1 0 Mode 2.
1 1 Mode 3.
SD BLANK Input 0 Enabled.
1 Disabled.
SD Luma Delay 0 0 No delay.
0 1 2 clock cycles.
1 0 4 clock cycles.
1 1 6 clock cycles.
SD Min. Luma Value 0 −40 IRE.
1 −7.5 IRE.
SD Timing Reset x 0 0 0 0 0 0 0 A low-high-low transition resets
the internal SD timing counters.
0x4B
SD
HSYNC
Width
0
0
T
a
= 1 clock cycle.
0x00
SD Timing
Register 1
0 1 T
a
= 4 clock cycles.
1 0 T
a
= 16 clock cycles.
1 1 T
a
= 128 clock cycles.
0
0
T
b
= 0 clock cycle.
SD
HSYNC
to
VSYNC
Delay
0 1 T
b
= 4 clock cycles.
1 0 T
b
= 8 clock cycles.
1 1 T
b
= 18 clock cycles.
x
0
T
c
= T
b
.
SD
HSYNC
to
VSYNC
Rising Edge Delay
(Mode 1 Only)
x 1 T
c
= T
b
+ 32 µs.
0 0 1 clock cycle.
VSYNC
Width
(Mode 2 Only)
0 1 4 clock cycles.
1 0 16 clock cycles.
1 1 128 clock cycles.
0
0
0 clock cycles.
HSYNC
to Pixel
Data Adjust
0 1 1 clock cycle.
1 0 2 clock cycles.
1 1 3 clock cycles.
0x4C SD F
SC
Register 0
1
x x x x x x x x Subcarrier Frequency Bits 7 to 0.
0x1E
1
0x4D SD F
SC
Register 1 x x x x x x x x Subcarrier Frequency Bits 15 to 8. 0x7C
0x4E SD F
SC
Register 2 x x x x x x x x Subcarrier Frequency Bits 23 to 16. 0xF0
0x4F SD F
SC
Register 3 x x x x x x x x Subcarrier Frequency Bits 31 to 24. 0x21
0x50 SD F
SC
Phase x x x x x x x x Subcarrier Phase Bits 9 to 2. 0x00
0x51 SD Closed
Captioning
Extended Data on
Even Fields
x x x x x x x x Extended Data Bits 7 to 0. 0x00
0x52 SD Closed
Captioning
Extended Data on
Even Fields
x x x x x x x x Extended Data Bits 15 to 8. 0x00
0x53 SD Closed
Captioning
Data on Odd Fields x x x x x x x x Data Bits 7 to 0. 0x00
0x54 SD Closed
Captioning
Data on Odd Fields x x x x x x x x Data Bits 15 to 8. 0x00
0x55 SD Pedestal
Register 0
Pedestal on Odd Fields 17 16 15 14 13 12 11 10 Setting any of these bits to 1
disables pedestal on the line num-
ber indicated by the bit settings.
0x00
0x56 SD Pedestal
Register 1
Pedestal on Odd Fields 25 24 23 22 21 20 19 18 0x00
0x57 SD Pedestal
Register 2
Pedestal on Even Fields 17 16 15 14 13 12 11 10 0x00
0x58 SD Pedestal
Register 3
Pedestal on Even Fields 25 24 23 22 21 20 19 18 0x00
1
For precise NTSC F
SC
, this register should be programmed to 0x1F.
LINE 313 LINE 314LINE 1
t
B
t
A
t
C
05067-024
HSYNC
VSYNC
Figure 48. Timing Register 1 in PAL Mode