Datasheet

ADV7320/ADV7321
Rev. A | Page 32 of 88
Table 15. Registers 0x3E to 0x43
SR7–
SR0
Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
Values
0x3E Reserved 0x00
0x3F Reserved 0x00
0 0 NTSC. 0x00
0 1 PAL B, D, G, H, I.
1 0 PAL M.
SD Standard
1 1 PAL N.
0 0 0 LPF NTSC.
0 0 1 LPF PAL.
0 1 0 Notch NTSC.
0 1 1 Notch PAL.
1 0 0 SSAF luma.
1 0 1 Luma CIF.
1 1 0 Luma QCIF.
SD Luma Filter
1 1 1 Reserved.
0 0 0 1.3 MHz.
0 0 1 0.65 MHz.
0 1 0 1.0 MHz.
0 1 1 2.0 MHz.
1 0 0 Reserved.
1 0 1 Chroma CIF.
1 1 0 Chroma QCIF.
0x40 SD Mode Register 0
SD Chroma Filter
1 1 1 3.0 MHz.
0x41 Reserved 0x00
0 Disabled. SD PrPb SSAF
1 Enabled.
0x08
0 Refer to the Output
Configuration section.
SD DAC Output 1
1
0 Refer to the Output
Configuration section.
SD DAC Output 2
1
0 Disabled. SD Pedestal
1 Enabled.
0 Disabled. SD Square Pixel
1 Enabled.
0 Disabled. SD VCR FF/RW Sync
1 Enabled.
0 Disabled. SD Pixel Data Valid
1 Enabled.
0 Disabled.
0x42 SD Mode Register 1
SD SAV/EAV Step
Edge Control
1 Enabled.
0 No pedestal on YUV. SD Pedestal YPrPb
Output
1 7.5 IRE pedestal on YUV.
0x00
0 Y = 700 mV/300 mV. SD Output Levels Y
1 Y = 714 mV/286 mV.
0 0 700 mV p-p (PAL);
1000 mV p-p (NTSC).
0 1 700 mV p-p.
1 0 1000 mV p-p.
SD Output Levels PrPb
1 1 648 mV p-p.
0 Disabled. SD VBI Open
1 Enabled.
0 0 CC disabled.
0 1 CC on odd field only.
1 0 CC on even field only.
SD CC Field Control
1 1 CC on both fields.
0x43 SD Mode Register 2
Reserved 0 Reserved.