Datasheet

ADV7320/ADV7321

Rev. A | Page 29 of 88

Table 12. Register 0x15

SR7–

SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

Reset

Values

0x15 Reserved 0 0 must be written to this bit. 0x00

HD Mode

HD RGB Input 0 Disabled.

1 Enabled.

HD Sync on PrPb 0 Disabled.

1 Enabled.

HD Color DAC Swap 0 DAC E = Pb; DAC F = Pr.

1 DAC E = Pr; DAC F = Pb.

HD Gamma Curve A 0 Gamma Curve A.

HD Gamma Curve B 1 Gamma Curve B.

HD Gamma Curve Enable 0 Disabled.

1 Enabled.

HD Adaptive Filter Mode 0 Mode A.

1 Mode B.

HD Adaptive Filter Enable 0 Disabled.

1 Enabled.