Datasheet

ADV7320/ADV7321
Rev. A | Page 26 of 88
Table 8. Registers 0x02 to 0x0F
SR7–
SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values
0x02 Mode Register 0 Reserved 0 0 0 must be written to these
bits.
0x20
0 Disabled.
Test Pattern Black
Bar 1 Enabled.
0x11, Bit 2 must
also be enabled.
Manual RGB Matrix
Adjust
0 Disable manual RGB
matrix adjust.
1 Enable manual RGB
matrix adjust.
Sync on RGB
1
0 No sync.
1 Sync on all RGB outputs.
RGB/YPrPb Output 0 RGB component outputs.
1 YPrPb component
outputs.
SD Sync 0 No sync output.
1 Output SD syncs on
S_HSYNC
,
S_VSYNC
,
S_BLANK
pins.
HD Sync 0 No sync output.
1 Output HD, ED, syncs on
S_HSYNC
,
S_VSYNC
.
0x03 RGB Matrix 0 x x LSB for GY. 0x03
0x04 RGB Matrix 1 x x LSB for RV. 0xF0
x x LSB for BU.
x x LSB for GV.
x x LSB for GU.
0x05 RGB Matrix 2 x x x x x x x x Bits 9 to 2 for GY. 0x4E
0x06 RGB Matrix 3 x x x x x x x x Bits 9 to 2 for GU. 0x0E
0x07 RGB Matrix 4 x x x x x x x x Bits 9 to 2 for GV. 0x24
0x08 RGB Matrix 5 x x x x x x x x Bits 9 to 2 for BU. 0x92
0x09 RGB Matrix 6 x x x x x x x x Bits 9 to 2 for RV. 0x7C
0x0A 0 0 0 0 0 0 0 0 0% 0x00
DAC A, B, C
Output Level
2
0 0 0 0 0 0 0 1 +0.018%
0 0 0 0 0 0 1 0 +0.036%
… …
0 0 1 1 1 1 1 1 +7.382%
Positive Gain to
DAC Output
Voltage
0 1 0 0 0 0 0 0 +7.5%
1 1 0 0 0 0 0 0 −7.5%
1 1 0 0 0 0 0 1 −7.382%
1 0 0 0 0 0 1 0 −7.364%
… …
Negative Gain to
DAC Output
Voltage
1 1 1 1 1 1 1 1 −0.018%
0x0B 0 0 0 0 0 0 0 0 0% 0x00
DAC D, E, F
Output Level
0 0 0 0 0 0 0 1 +0.018%
0 0 0 0 0 0 1 0 +0.036%
… …
0 0 1 1 1 1 1 1 +7.382%
Positive Gain to
DAC Output
Voltage
0 1 0 0 0 0 0 0 +7.5%
1 1 0 0 0 0 0 0 −7.5%
1 1 0 0 0 0 0 1 −7.382%
1 0 0 0 0 0 1 0 −7.364%
… …
Negative Gain to
DAC Output
Voltage
1 1 1 1 1 1 1 1 −0.018%
0x0C Reserved 0x00
0x0D Reserved 0x00
0x0E Reserved 0x00
0x0F Reserved 0x00
1
For more detail, refer to Appendix 7.
2
For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.